eISSN: 2791-173X editor@grpublishing.org
All Journals
Submit your article

Global Multidisciplinary Journal

Open Access Peer Review International
Open Access

An Analysis of Fault-Tolerant Dual-Core Lockstep Architectures and Soft Error Mitigation Strategies in High-Reliability Semiconductor Systems

DOI
PDF
Marcus Snowden 1 ,
4 Department of Electrical and Computer Engineering, University of Manchester, United Kingdom

Abstract

This research provides an exhaustive investigation into the architectural paradigms and mitigation strategies required to ensure reliability in advanced semiconductor technologies, specifically focusing on SRAM-based Field Programmable Gate Arrays (FPGAs) and multi-core processor environments. As transistor dimensions continue to shrink into the sub-nanometer regime, the susceptibility of integrated circuits to radiation-induced soft errors, such as Single Event Upsets (SEUs), has increased exponentially. This article synthesizes foundational theories of fault tolerance with contemporary implementation techniques, including Triple Module Redundancy (TMR), Dual-Core Lockstep (DCLS) configurations, and hybrid non-intrusive error detection. By analyzing the intersection of safety-critical automotive zonal controllers and nuclear instrumentation systems, the study evaluates the trade-offs between hardware overhead, latency, and error coverage. The methodology adopts a descriptive analytical approach, detailing the evolution from traditional redundancy to advanced algorithmic-based fault tolerance and control-flow monitoring. Findings suggest that while hardware redundancy remains the gold standard for spatial applications, hybrid software-hardware approaches offer a more power-efficient solution for terrestrial automotive and industrial sectors. The discussion further explores the shift toward zonal control in vehicular networks, emphasizing the necessity of timely error detection to maintain functional safety in autonomous systems.

Keywords

Fault Tolerance, Soft Errors, Dual-Core Lockstep, SRAM-FPGA

References

📄 Abdul Salam Abdul Karim. (2023). Fault-Tolerant Dual-Core Lockstep Architecture for Automotive Zonal Controllers Using NXP S32G Processors. International Journal of Intelligent Systems and Applications in Engineering, 11(11s), 877–885. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/7749
📄 Avizienis, A. (1976). Fault-tolerant systems. IEEE Transactions on Computers, 25(12), 1304–1312.
📄 Azambuja, J. R., Altieri, M., Becker, J., and Kastensmidt, F. L. (2013). HETA: hybrid error-detection technique using assertions. IEEE Transactions on Nuclear Science, 60(4), 2805–2812.
📄 Baumann, R. C. (2005). Radiation-induced soft errors in advanced semiconductor technologies. IEEE Transactions on Device and Materials Reliability, 5(3).
📄 Carmichael, C. (2006). Triple Module Redundancy Design Techniques for Virtex FPGAs. Xilinx Inc., San Jose, CA, USA. XAPP197 Application Note.
📄 Gomaa, M., Scarbrough, C., Vijaykumar, T. N., and Pomeranz, I. (2003). Transient-fault recovery for chip multiprocessors. Proceedings of the International Symposium on Computer Architecture.
📄 Hernandez, C., and Abella, J. (2014). LiVe: Timely error detection in light lockstep safetycritical systems. Design Automation Conference.
📄 Huang, K. H., and Abraham, J. A. (1984). Algorithm-based fault tolerance for matrix operations. IEEE Transactions on Computers, C-33(6), 518–528.
📄 Kasap, S., Weber Wächter, E., Zhai, X., Ehsan, S., and Mcdonald-Maier, K. (2020). Survey of soft error mitigation techniques applied to LEON3 soft processors on SRAM-based FPGAs. IEEE Access, 8, 28646–28658.
📄 Nidhin, T., Bhattacharyya, A., Behera, R., Jayanthi, T., and Velusamy, K. (2017). Understanding radiation effects in SRAM-based field programmable gate arrays for implementing instrumentation and control systems of nuclear power plants. Nuclear Engineering and Technology, 49(8), 1589-1599.
📄 Parra, L., Lindoso, A., Portela-Garcia, M., Entrena, L., Du, B., Reorda, M. S., and Sterpone, L. (2014). A new hybrid nonintrusive error-detection technique using dual control-flow monitoring. IEEE Transactions on Nuclear Science, 61(6), 3236-3243.
📄 Quinn, H., Baker, Z., Fairbanks, T., Tripp, J. L., and Duran, G. (2017). Robust duplication with comparison methods in microcontrollers. IEEE Transactions on Nuclear Science, 64(1), 338-345.
📄 Wirthlin, M. (2015). High-reliability FPGA-based systems: space, high-energy physics, and beyond. Proceedings of the IEEE, 103(3), 379-389.

How to Cite

Marcus Snowden. (2024). An Analysis of Fault-Tolerant Dual-Core Lockstep Architectures and Soft Error Mitigation Strategies in High-Reliability Semiconductor Systems. Global Multidisciplinary Journal, 3(10), 12-17. https://www.grpublishing.org/journals/index.php/gmj/article/view/376

Most read articles by the same author(s)

<< < 1 2 3 4 5 6 7 8 9 10 > >> 

Similar Articles

1-10 of 25

You may also start an advanced similarity search for this article.