[1]
Marcus Snowden, “An Analysis of Fault-Tolerant Dual-Core Lockstep Architectures and Soft Error Mitigation Strategies in High-Reliability Semiconductor Systems”, gmj, vol. 3, no. 10, pp. 12–17, Oct. 2024, Accessed: Mar. 28, 2026. [Online]. Available: https://www.grpublishing.org/journals/index.php/gmj/article/view/376